The present invention relates to a memory cell configuration with read/write protection.
In the case of programmable integrated circuits, for example in the case of calibratable sensors, it may be desirable to protect the memory content of a nonvolatile memory after the one-time programming thereof in such a way that change or erasure is impossible.
U.S. Pat. No. 6,041,007 specifies an integrated circuit, preferably an electronic sensor, with a programmable memory cell designed as an EEPROM (Electrically Erasable Programmable Read Only Memory). In order to latch the memory cell, a latching memory cell is provided, which can be overwritten only when a signal that can be fed in externally is present.
Reprogramming of the programmable memory cells is no longer possible after the conclusion of production.
One possibility for protecting the memory content consists in setting a write protection bit for latching the memory at the end of a one-time programming. This makes it possible to prevent further programming or activation of test routines and to latch a data input present at the integrated circuit. It is thus ensured that only one operating state, the so-called normal operating mode, can be implemented after the conclusion of programming and after the setting of the latching bit.
By way of example, by applying an overvoltage to voltage supply terminals of the integrated circuit, it is usually possible to change from the normal operating mode to other modes, for example to a write mode, in which data are written to a nonvolatile memory. Furthermore, a test mode may be provided which enables a read-out of the nonvolatile memory, so that, by way of example, after each operation of writing a bit to the nonvolatile memory, it is possible to check whether this write operation has been effected in a manner free of errors.
In this case, however, the problem arises that if the latching bit is set in the nonvolatile memory, it is no longer possible to check that the write operation is free from errors, since only the normal operating mode can be implemented after the setting of the latching bit. The normal operating mode does not permit any test or read modes.
In particular, the problem can arise that when the latching bit is written in the nonvolatile memory, further memory cells of the nonvolatile memory are written to inadvertently. Such incorrect programming can remain undiscovered even in the event of extensive functional tests.
It is accordingly an object of the invention to provide a memory cell configuration that overcomes the above-mentioned disadvantages of the prior art apparatus of this general type.
In particular, it is an object of the invention to provide a memory cell configuration in which latching of a nonvolatile memory is provided and in which the correct programming of a latched memory area can be checked.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell configuration including: a nonvolatile memory including a latching memory cell for indicating a read protection and/or a write protection of the nonvolatile memory; a latching element for preventing read operations and/or write operations on the nonvolatile memory, the latching element coupled to the nonvolatile memory; and an additional memory element having an input coupled to the latching memory cell and an output connected to the latching element for driving the latching element.
In accordance with an added feature of the invention, the configuration includes an activation element for receiving an activation signal. The activation element provides information stored in the latching memory cell to the additional memory element, dependent on the activation signal.
In accordance with an additional feature of the invention, the configuration includes an OR gate having an output, a first input for receiving a switch-on phase indicator signal, and a second input for receiving a normal operating mode indicator signal. The activation element has an input connected to the output of the OR gate.
In accordance with another feature of the invention, the configuration includes a decoding block having an output connected to the second input of the OR gate. The decoding block provides the normal operating mode indicator signal to the OR gate.
In accordance with a further feature of the invention, the configuration includes a D-type flip-flop including the activation element and the additional memory element.
In accordance with another added feature of the invention, the configuration includes a volatile memory having an output connected to the nonvolatile memory. The volatile memory has a data input.
In accordance with another additional feature of the invention, the volatile memory area includes a test register.
In accordance with yet an added feature of the invention, the test register has a reset input, and the output of the additional memory element is connected to the reset input of the test register.
In the case of the memory cell configuration described, the latching of the nonvolatile memory is not effected directly by setting a bit thereof, but rather the latching is effected by the additional memory element coupled to the latching element of the nonvolatile memory. The provision of such a latched copy of the latching memory cell of the nonvolatile memory, which copy can carry the latching bit (memory lock bit), enables, by way of example, a time-delayed activation of the additional memory element.
By way of example, depending on an operating mode of the memory cell configuration, the memory content of the latching memory cell, which may be 1 bit, can be switched through to the output of the additional memory element and can be continuously refreshed in a normal operating mode.
This makes it possible first to avoid inadvertent programming of the nonvolatile memory during operation due to latching thereof and also to check the freedom from errors in the programming operation with regard to the latching memory cell with a latching bit itself.
In an advantageous embodiment of the present invention, an activation element is provided, which effects a provision of information stored in the latching memory cell in the additional memory element in a manner dependent on an activation signal that can be fed to the activation element.
By way of example, a switch-on phase indicator signal may be fed as an activation signal to the activation element. The indicator signal is active during a switch-on phase of the memory cell configuration, or during a switch-on phase of an integrated circuit including the memory cell configuration and thus indicates the switch-on phase.
By setting a latching bit in the latching memory cell, the nonvolatile memory in the memory cell configuration is thus latched only when the memory cell configuration is switched on a next time after a programming.
In a further advantageous embodiment of the present invention, an OR gate has an output connected to an input of the activation element, an input fed with a switch-on phase indicator signal, and another input fed with a normal operating mode indicator signal.
By feeding in a normal operating mode indicator signal in addition to a switch-on phase indicator signal, the nonvolatile memory can be latched as early as after the conclusion of the programming of the nonvolatile memory and the beginning of the normal operating mode of the memory cell configuration. The possibility of checking the nonvolatile memory for error-free programming is preserved here.
In a further advantageous embodiment of the present invention, a decoding block provides the normal operating mode indicator signal. The output of the decoding block is connected to an input of the OR gate.
The decoding block can decode, for example, an increased operating voltage, which indicates a mode other than a normal operating mode, and in the case of a normal operating mode, provides a normal operating mode indicator signal at its output.
In a further advantageous embodiment of the present invention, a D-type flip-flop is provided, which includes the activation element and the additional memory element.
A D-type flip-flop enables a simple and reliable possibility for realizing the additional memory element and the activation thereof with an activation signal that can be fed to the clock input of the D-type flip-flop. In this case, the D input of the D-type flip-flop can be coupled to the latching memory cell.
In a further advantageous embodiment of the present invention, a volatile memory is provided, which has a data input and an output connected to the nonvolatile memory.
The data input of the volatile memory may be embodied as a serial data input. The data can be transferred in parallel from the volatile memory, which may be embodied as a register, to the nonvolatile memory. The latching element may be connected to the data input.
In a further advantageous embodiment of the present invention, the memory area of the volatile memory includes a test register. The test register may be required in a test mode.
In a further advantageous embodiment of the present invention, the output of the additional memory element is connected to a reset input of the test register. If a test register that can indicate an active test mode is provided, it is advantageous to reset the test register when the additional memory element is activated. In this case, the data input of the volatile memory can be latched at the same time.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory cell configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.